The present invention relates generally to semiconductor devices and semiconductor manufacturing and, more particularly, to semiconductor devices using silicide processes generally and in connection with efforts to inhibit reverse engineering.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors, etc.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. While the particular structure of a given active device can vary between device types, a MOS-type transistor generally includes heavily doped diffusion regions, referred to as source and drain regions, and a gate electrode that modulates current flowing in a channel between the source and drain regions.
One important step in the manufacturing of such devices is the formation of isolation areas to electrically separate electrical devices or portions thereof that are closely integrated in the silicon wafer. Typically, current does not flow between active regions of adjacent MOS-type transistors. However, in certain circuit designs it is desirable to electrically link source/drain diffusions of adjacent MOS-type transistors. Such linking is useful in various circuit design applications including, for example, adjacent transistor circuits requiring resistive transistor intercoupling.
In circuit applications involving two diffusion regions of the same polarity type, such as two P+ doped adjacent regions in an N-well substrate area, the portion of the substrate area between the two adjacent regions can be used as an electrical insulator. More specifically, each heavily doped diffusion region and a portion of adjacent substrate act as a reverse-biased diode blocking the flow of electrons between the two diffusions. Conversely, the portion of the substrate area between the two adjacent regions can also be implemented to act as an electrical conductor. One way to implement such conduction is to effect the same polarity in the portion of the substrate area between the two adjacent regions as the polarity of the two adjacent regions. Accordingly, each adjacent heavily doped region can be doped simultaneously with the portion of the substrate area between the two adjacent regions to overcome the reverse-biased diode effect.
For many designers, linking two active regions of the same polarity type in this manner is desirable for preventing reverse engineering by competitors. Reverse engineering involves the use of analytical techniques, such as scanning-electron microscopy, to determine the design of an integrated circuit including identification of electrical connections between active regions. For many analytical techniques, including scanning-electron microscopy, linking and blocking connectivity between two active regions of the same polarity type, in the manner described above, appears identical and thereby undermines the typical reverse-engineering effort.
This approach is not readily achievable for all circuit architectures, particularly those involving salicide processes. Salicide processing refers to self-aligned silicide processing; in which metal is heat-reacted with silicon to form xe2x80x9csilicidexe2x80x9d over an active region to form contact regions over the silicide with minimal masking steps. In a salicide process, siliciding two heavily doped regions of the same polarity normally results in silicide forming over the portion of the substrate area between the two adjacent regions which, in turn, results in shorting the two heavily doped regions. Because the two adjacent regions are linked by the detectable silicide, typical reverse-engineering efforts can readily detect whether or not the adjacent heavily doped regions are electrically linked.
The present invention is exemplified in a number of implementations, some of which are summarized below. According to one embodiment, a method of fabricating a semiconductor device, includes first forming a dopable region between two heavily doped regions over a substrate region in the semiconductor device, with the substrate region doped to achieve a first polarity type, and with the two heavily doped regions doped to achieve a second polarity type that is opposite the first polarity type. The dopable region is adapted to selectively link the two active regions when doped to achieve the second polarity type. Further, over the dopable region and extending over a portion of each of the two heavily doped regions, a dielectric is formed that is adapted to inhibit silicide formation over edges of the dopable region and the structure is silicided adjacent the dielectric over another portion of at least one of the two heavily doped regions.
In another embodiment of the present invention, a semiconductor device, comprises: two heavily doped regions over a substrate region in the semiconductor device; a dopable region between the two heavily doped regions, the substrate region doped to achieve a first polarity type, wherein the two active regions are doped to achieve a second polarity type that is opposite the first polarity type, and wherein the dopable region is adapted to selectively link the two heavily doped regions when doped to achieve the second polarity type; a dielectric formed over the dopable region and extending over a portion of each of the two active regions, the dielectric adapted to inhibit silicide formation over edges of the dopable region; and a silicide formation adjacent the dielectric over another portion of at least one of the two heavily doped regions.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description that follow more particularly exemplify these embodiments.